outgoing buffer to provide buffering for the following:
- DirtyExclusive blocks that are cast out of the secondary cache because of a block replacement
- various CACHE instructions
- an external intervention request.
Four 32-word typical entries are associated with the four possible outstanding processor cached requests allowed by the processor. One 32-word special entry is reserved for external intervention requests only. The data is stored in each entry of the outgoing buffer in sequential order, beginning with a secondary cache block-aligned address.
An instruction or data access that misses in the secondary cache but targets an entry in the outgoing buffer is stalled until the outgoing buffer entry is issued as a processor block write request or coherency data response to the System interface bus.
External coherency requests probe the four typical outgoing buffer entries, with the following results:
- If an external intervention request hits a typical entry, that entry is converted from a processor block write request to a processor coherency data response.
- If an external invalidate request hits a typical outgoing buffer entry, that entry is deleted.
- If an external intervention request does not hit a typical outgoing buffer entry, but hits a DirtyExclusive block in the secondary cache, the special outgoing buffer entry is used to buffer the processor coherency data response.
A typical outgoing buffer entry containing a block write is ready for issue to the System interface bus when the first quadword is received from the secondary cache. The processor allows data to stream from the secondary cache to the System interface bus through the outgoing buffer.
